1. Field
Example embodiments relate to a semiconductor memory device, and more particularly, to a semiconductor memory device that includes a memory cell array with a floating body transistor using a bipolar junction transistor operation, and writes and reads data by generating a variable reference voltage.
2. Description of Related Art
In general, a dynamic memory cell includes one access transistor and one data storage capacitor. Data “1” is stored when charges are stored in the capacitor and data “0” is stored when no charge is stored in the capacitor. Since the charges stored in the capacitor are lost after a given time has elapsed, a refresh operation should be performed. When a memory cell array is configured with the memory cell, there is a limit to reducing a layout area of a semiconductor memory device.
To reduce the layout area of the semiconductor memory device, a transistor with a floating body has been recently proposed. This transistor stores majority carriers in the floating body. Since the stored majority carriers are also lost when a given time has elapsed, a refresh operation should be performed. Since a memory cell configured by the transistor with the floating body does not have a capacitor, as opposed to a general memory cell, but still operates like the capacitor, such a memory cell is used as a dynamic memory cell. A semiconductor memory device with such a dynamic memory cell has a smaller layout area than a semiconductor memory device with the general memory cell.
There are ongoing efforts to increase the operation speed and data retention characteristics of a memory cell array with a dynamic memory cell using a floating body transistor by using a bipolar junction transistor operation of the floating body transistor.
FIG. 1 illustrates an equivalent circuit diagram of a structure of a conventional floating body transistor. The floating body transistor includes an n-channel metal oxide semiconductor (NMOS) field-effect transistor (hereinafter, referred to as an NMOS transistor) and an NPN bipolar junction transistor (hereinafter, referred to as an NPN transistor). A source S of the NMOS transistor and an emitter E of the NPN transistor are shared. A drain D of the NMOS transistor and a collector C of the NPN transistor are shared. A base B of the NPN transistor is floated. A coupling capacitor CC exists between a gate G and a base B of the NMOS transistor.
A data “1” state is a state in which majority carriers, i.e., holes, are accumulated in a floating body region. A data “0” state is a state in which minority carriers, i.e., electrons, are accumulated in the floating body region.
When a gate voltage Vg is 0 V, the floating body transistor has a rapid current increase before a voltage Vds between the drain and the source is equal to or higher than a predetermined level, regardless of the data “1” or “0” state. According to the above-described rapid current increase, holes enter the base B by initial drain coupling when a voltage difference Vds between the drain and the source is more than a given voltage. When a potential of the base region increases, a forward voltage is applied between the base B and the emitter E, inducing an emitter current. A large emitter current flows into the collector C. This current passes through a band bending region between the base B and the collector C, leading to band-to-band tunneling and/or impact ionization.
Holes are injected from the collector C to the base B by the band-to-band tunneling and/or impact ionization, causing the potential of the base B to increase once more. When the voltage Vds between the drain and the source increases and the NPN transistor is turned on, a bipolar current Ids is rapidly increased by a forward feedback system of the NPN transistor itself. When a multiplication factor is increased by the impact ionization, the bipolar current Ids may be increased rapidly.
In the case of a negative gate voltage Vg, compared with the gate voltage Vg of 0 V, the bipolar current increases rapidly at a relatively high voltage Vds between the drain and the source. When the gate voltage Vg decreases, a positive electric potential of the base decreases. Accordingly, the NPN transistor may be turned on by the band-to-band tunneling and/or impact ionization only when the voltage Vds between the drain and the source increases.
Meanwhile, another topic of active research is a bit line sense amplification circuit for performing a bipolar junction transistor operation and a semiconductor memory device for securing a margin capable of sensing a current difference by adaptively varying a data ground voltage of a memory cell according to ambient temperature variation, among semiconductor memory devices that have a memory cell with a floating body and perform data write and read operations.
FIG. 2 illustrates a partial block diagram of data write and read operations of a conventional semiconductor memory device including a memory cell with a floating body. The conventional semiconductor memory device includes a memory cell array block BLK1, a bit line selector 10-11, a reference bit line selector 12-1, level limiters 14-1 to 14-(m−1), a sense amplifier 16-1, a reference voltage generator 18, a comparator COM1, a latch LA1, a write back gate WBG1, a read column select gate RG1, a write column select gate WG1, and a reference write column select gate RWG.
In FIG. 2, only some components are shown while others have been omitted for convenience. In FIG. 2, only bit lines BL1 to BLj, which may be open or folded type bit lines, are arranged to the left of the sense amplifier, and inverted bit lines BL1B to BLjB have been omitted.
Now, write and read operations of the semiconductor memory device shown in FIG. 2 will be described.
First, a write operation of reference memory cells RMC will be described.
When a word line WL11 is activated, a voltage of about 1.5 V is applied, and a reference bit line select signal RBS1 is activated, a reference bit line RBL1 is connected to a reference sense bit line RSBL. When a reference write column select signal RWCSL is activated, an NMOS transistor N7 is turned on and therefore data to be output to a write data line WD is output to the reference bit line RBL1 through the reference sense bit line RSBL. Data “1” is written to all reference memory cells RMC connected between word lines WL11 and WL21 and reference bit lines RBL2.
In order to generate a reference voltage VREF during a data read operation, data “0” is written to reference memory cells RMC connected to the reference bit line RBL1 of each of reference memory cell array blocks RBLK1 and RBLK2, and data “1” is written to reference memory cells RMC connected to the reference bit line RBL2.
Next, a write operation of memory cells MC will be described.
When a voltage of about 1.5 V is applied to the word line WL11 and a bit line select signal BS1 is activated, a bit line BL1 is connected to a sense bit line SBL1. When a write column select signal WCSL1 is activated, an NMOS transistor N6 is turned on. When a voltage of −1.5 V is applied to a write data line WD, this voltage is output to the bit line BL1 through the sense bit line SBL1 and data “0” is written to a memory cell MC between the word line WL11 and the bit line BL1. When a voltage of 1.5 V is applied to the write data line WD, data “1” is written.
Now, a read operation of the memory cells MC will be described.
When a voltage of about 1.5 V is applied to the word line WL11 and the bit line select signal BS1 is activated, the bit line BL1 is connected to the sense bit line SBL1 and a signal is output from the bit line BL1 to the sense bit line SBL1. At this time, the reference bit line select signals RBS1 and RBS2 are simultaneously activated. Accordingly, the reference bit lines RBL1 and RBL2 are connected to the reference sense bit line RSBL and signals are output from the reference bit lines RBL1 and RBL2 to the reference sense bit line RSBL.
The level limiter 14-1 prevents a current from flowing from an output node “a1” to the sense bit line SBL1 when a voltage of the sense bit line SBL1 is higher than a limited voltage VBLR due to a current flowing into the sense bit line SBL1, thereby enabling the sense bit line SBL1 to be maintained at a voltage less than the limited voltage VBLR. When a current Ic1 corresponding to data stored in the memory cell MC is generated, the sense amplifier 16-1 senses the current Ic1 and generates a sensed voltage Sn1.
When the reference voltage generator 18 senses the current Ic(m+1) and generates a reference voltage VREF between a voltage corresponding to the data “0” and a voltage corresponding to the data “1” output from the sense amplifier 16-1, the comparator COM1 is enabled in response to a sense-amplifier enable signal SEN, compares the sensed voltage Sn1 generated by the sense amplifier 16-1 with the reference voltage VREF, and generates sensed data.
That is, when the sensed voltage Sn1 generated by the sense amplifier 16-1 is lower than the reference voltage VREF, the comparator COM1 outputs a high-level signal to a corresponding node “a”. Conversely, when the sensed voltage Sn1 is higher than the reference voltage VREF, the comparator COM1 outputs a low-level signal to the corresponding node “a”.
The latch LA1 latches the sensed data. When a read column select signal RCSL1 is activated, NMOS transistors N2 and N4 are turned on. In this case, when the node “a” is at a high level, an NMOS transistor N5 is turned on and outputs low-level data to an inverted read data line RDB. Meanwhile, when a node “b” is at a high level, an NMOS transistor N3 is turned on and outputs the low-level data to a read data line RD. That is, the low-level data is output to the read data line RD or the inverted read data line RDB during the read operation.
In a conventional semiconductor memory device that includes a memory cell with a floating body and performs data write and read operations, there is a problem in that the size of a bit line sense amplifier must be increased to generate a reference voltage for bit line sense amplification when a reference voltage generator is included in the bit line sense amplifier, and the size of a memory array increases since a dummy cell configured with reference memory cells RMC is added to the memory array.
There is another problem in that a control operation for enabling a dummy cell is additionally needed to enable reference memory cells RMC, and complex circuits of a level limiter, a comparator, a latch, a write back gate, a read column select gate RG1, a write column select gate WG1, a reference write column select gate RWG, etc. are needed for the data read operation.
Meanwhile, since a reference voltage generation method of the conventional floating body transistor is not adaptive to variation of drain-source current Ids because a fixed voltage value of a middle level between an internal voltage VINTA and a ground voltage VSS is used as a reference voltage of bit line sensing, a bit line sense amplifier may not stably and accurately detect a current difference.
Even when direct current (DC) characteristics of a floating body transistor are varied in an abnormal situation in which an ambient temperature is significantly different from room temperature, the semiconductor memory device uses a fixed voltage value as a reference voltage for bit line sensing regardless of variation in the ambient temperature. Accordingly, since a margin of a difference between drain-source currents for generating the data “0” and the data “1” is very small, it is difficult to secure a sufficient margin capable of stably sensing the current difference. Therefore, there is a problem in that a read operation of the semiconductor memory device may malfunction.